Advanced Chip Engineering Design and Fabrication

Due Date
Where the Opportunity is Offered
All of California
Eligible Applicant
Additional Eligibility Information
*Who May Submit Proposals: Proposals may only be submitted by the following: -Institutions of Higher Education (IHEs) - Two- and four-year IHEs (including community colleges) accredited in, and having a campus located in the US, acting on behalf of their faculty members.Special Instructions for International Branch Campuses of US IHEs: If the proposal includes funding to be provided to an international branch campus of a US institution of higher education (including through use of subawards and consultant arrangements), the proposer must explain the benefit(s) to the project of performance at the international branch campus, and justify why the project activities cannot be performed at the US campus. *Who May Serve as PI: U.S. PIs must hold primary, full-time, paid appointments in research or teaching positions at U.S.-based campuses/offices of IHEs eligible to submit to this solicitation. Each proposal must include at least one U.S.-eligible researcher as lead PI and at least one Taiwan-eligible researcher as senior personnel (non-funded). PIs, co-PIs, and senior personnel of a <span>Research Coordination Network</span>award designated to support this program (see priority A in <a href="">NSF 22-116</a>) are not eligible to submit proposals under this proposal cycle of the ACED Fab program.
NSF support

The Directorate for Engineering (ENG), Division of Electrical, Communications and Cyber Systems (ECCS), Division of Chemical, Bioengineering, Environmental, and Transport Systems (CBET), Division of Civil, Mechanical and Manufacturing Innovation (CMMI), Division of Engineering Education and Centers (EEC), and The Office of International Science and Engineering(OISE) of the National Science Foundation (NSF) and the Department of Engineering and Technologies (DET) of the Taiwan National Science and Technology Council (NSTC) are pleased to announce and launch an NSF-NSTC semiconductor collaboration program titled “Advanced Chip Engineering Design and Fabrication (ACED Fab)”. This program aims to leverage the complementary academic talent and engineering strengths of semiconductor research in the U.S. and Taiwan to enable chip design and fabrication to advance semiconductor science, engineering, and education. This partnership program is guided by the Memorandum of Understanding (MOU) and Implementing Arrangement for Cooperation in Advanced Semiconductor Chip Design and Fabrication signed by the American Institute in Taiwan (AIT) and the Taipei Economic and Cultural Representative Office in the United States (TECRO). The MOU provides guidelines for a collaborative arrangement whereby U.S. researchers may receive funding from NSF and Taiwan researchers may receive funding from the Taiwan National Science and Technology Council (NSTC). Through a lead agency model, NSF and NSTC, as AIT and TECRO’s Designated Representatives under the MOU, respectively, invite U.S. and Taiwan researchers to submit a single collaborative proposal that will undergo a single review process at NSF, which will be the lead agency. NSTC will honor the NSF merit review process and will coordinate with NSF on award decisions. Awards to researchers in the U.S. and Taiwan will be issued in parallel by NSF and NSTC, respectively. The ACED Fab supports innovative design and fabrication projects of semiconductor chips utilizing advanced technologies of Taiwan’s semiconductor foundries. Proposals are encouraged to target emerging applications (but not limited to): High-performance, low-power circuits and systems; Edge-AI sensing, computing, and communication; Quantum computing and communication chips; and Emerging semiconductor heterogeneous integration. An ACED Fab proposal must be an integrated collaborative effort between the U.S. and Taiwan researchers. The research project must aim to bring a specific innovation to integrated circuit prototypes that demonstrate advanced functionality and utilize advanced fabrication technology as differentiators. The scope of an ACED Fab proposal must include at least one semiconductor chip design for tape-out utilizing fabrication process technologies of Taiwan’s semiconductor foundries via multi-project wafer runs within the duration of the project. General and specific inquiries regarding this funding opportunity are directed to Taiwan researchers are invited to read the NSTC announcement at The NSTC website indicates the funding limits for Taiwan researchers in this ACED Fab collaborative program. NSTC’s support for Taiwan researchers will be for the duration approved by NSF for the U.S. grantees of the same team.

Last Updated